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  • EPM7256SQC208-10

EPM7256SQC208-10

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Manufacturer No:

EPM7256SQC208-10

Manufacturer:

Altera

HK JDW NO:

2936-EPM7256SQC208-10

Package:

PQFP

Datasheet:

EPM7256SQC208-10

Description:

3.3/55V 0.5mm PMIC 208 Pin 125MHz 5V PQFP

Quantity:

In Stock : 999

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EPM7256SQC208-10 Overview


There are 256 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).The product is contained in a PQFP package.This device has 164 I/O ports programmed into it.There are 208 terminations programmed into the device.The terminal position of this electrical component is QUAD.There is 5V voltage supply for this device.There is a part included in Programmable Logic Devices.It is recommended to package the chip by Bulk.In this chip, the 208pins are programmed.5000gates are devices that serve as building blocks for digital circuits.Data storage is performed using [0].In this case, it is mounted by Surface Mount.A total of 208pins are provided on this board.With a maximum supply voltage of [0], it operates.Normally, it operates with a voltage of 3VV as its minimum supply voltage.There is 3.3/55V power supply available for it.In total, there are 164programmable I/Os.It is possible to achieve a frequency of 125MHz.It is recommended that the operating temperature exceed 0°C.A temperature lower than 70°Cis recommended for operation.The program consists of 16 logic blocks (LABs).The maximum frequency should not exceed 128.2MHz.It is possible to classify programmable logic as EE PLD.

EPM7256SQC208-10 Features


PQFP package
164 I/Os
208 pin count
208 pins
3.3/55V power supplies
16 logic blocks (LABs)

EPM7256SQC208-10 Applications


There are a lot of Altera EPM7256SQC208-10 CPLDs applications.

  • SUPERVISORY FUNCTION (LVD AND WATCHDOG)
  • Boolean function generators
  • Synchronous or asynchronous mode
  • Configurable Addressing of I/O Boards
  • Parity generators
  • ON-CHIP OSCILLATOR CIRCUIT
  • POWER-SAVING MODES
  • Interface bridging
  • Portable digital devices
  • Custom shift registers
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Package

Product
Step1Product
Casing drivepipe
Step2Casing drivepipe
Anti-static bag
Step3Anti-static bag
Packaging boxes
Step4Packaging boxes
Bar-code shipping tag
Step5Bar-code shipping tag

EPM7256SQC208-10

technical specifications, attributes, parameters and parts with similar specifications to EPM7256SQC208-10.

  • Type
    Parameter
    Select All
  • Mount

    Surface Mount

  • Package / Case

    PQFP

  • Number of Pins

    208

  • Packaging

    Bulk

  • Published

    1998

  • JESD-609 Code

    e0

  • Pbfree Code

    no

  • Moisture Sensitivity Level (MSL)

    3

  • Number of Terminations

    208

  • Terminal Finish

    Tin/Lead (Sn/Pb)

  • Max Operating Temperature

    70°C

  • Min Operating Temperature

    0°C

  • HTS Code

    8542.39.00.01

  • Subcategory

    Programmable Logic Devices

  • Technology

    CMOS

  • Terminal Position

    QUAD

  • Terminal Form

    GULL WING

  • Peak Reflow Temperature (Cel)

    220

  • Supply Voltage

    5V

  • Terminal Pitch

    0.5mm

  • Frequency

    125MHz

  • Time@Peak Reflow Temperature-Max (s)

    30

  • Pin Count

    208

  • Qualification Status

    Not Qualified

  • Power Supplies

    3.3/55V

  • Temperature Grade

    COMMERCIAL

  • Max Supply Voltage

    3.6V

  • Min Supply Voltage

    3V

  • Number of I/O

    164

  • Memory Type

    EEPROM

  • Propagation Delay

    10 ns

  • Turn On Delay Time

    10 ns

  • Frequency (Max)

    128.2MHz

  • Programmable Logic Type

    EE PLD

  • Number of Gates

    5000

  • Number of Programmable I/O

    164

  • Number of Logic Blocks (LABs)

    16

  • Speed Grade

    10

  • Output Function

    MACROCELL

  • Number of Macro Cells

    256

  • JTAG BST

    YES

  • In-System Programmable

    YES

  • Height Seated (Max)

    4.1mm

  • Length

    28mm

  • Width

    28mm

  • RoHS Status

    RoHS Compliant

  • Lead Free

    Contains Lead

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