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  • EPM7256ERC208-20

EPM7256ERC208-20

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Manufacturer No:

EPM7256ERC208-20

Manufacturer:

Altera

HK JDW NO:

2936-EPM7256ERC208-20

Package:

QFP

Datasheet:

EPM7256ERC208-20

Description:

0.5mm PMIC 208 Pin 83.33MHz 5V QFP

Quantity:

In Stock : 999

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EPM7256ERC208-20 Overview


A mobile phone network consists of 256macro cells, which are radio coverage cells served by a high-power cell site (tower, antenna or mast).In the QFPpackage, you will find it.There are 164 I/Os programmed in it.The termination of a device is set to [0].Its terminal position is QUAD.It is powered from a supply voltage of 5V.There is a part included in Programmable Logic Devices.There are 208 pins on the chip.This device is also capable of displaying [0].5000gates are devices that serve as building blocks for digital circuits.In order to maintain high efficiency, the supply voltage should be maintained at [0].In this case, EEPROMwill be used to store the data.The electronic component is mounted by Surface Mount.It is designed with 208 pins.This device operates at a voltage of 5.25Vas its maximum supply voltage.Despite its minimal supply voltage of [0], it is capable of operating.Programmable I/Os are counted up 164.This frequency is 83.33MHz.Operating temperatures should be higher than 0°C.Temperatures should not exceed 70°C.The system consists of 16 logic blocks (LABs).It is recommended that the maximal frequency be lower than 90.9MHz.A programmable logic type can be categorized as EE PLD.

EPM7256ERC208-20 Features


QFP package
164 I/Os
208 pin count
208 pins
16 logic blocks (LABs)

EPM7256ERC208-20 Applications


There are a lot of Altera EPM7256ERC208-20 CPLDs applications.

  • Multiple Clock Source Selection
  • Digital systems
  • ON-CHIP OSCILLATOR CIRCUIT
  • DMA control
  • I2C BUS INTERFACE
  • ROM patching
  • ToR/Aggregation/Core Switch and Router
  • State machine design
  • White goods (Washing, Cold, Aircon ,...)
  • Interface bridging
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EmailEmail for receiving inquiries: jindawei@hkjdwchip.com

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4. Shipping Cost

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Payment Method

The fee is charged according to the rule of PayPal.
East West Bank charge US$30.00 banking fee.
The fee is charged according to the rule of PayPal.
Western Union charge US$0.00 banking fee.

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UPS(www.ups.com)
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FedEx(www.fedex.com)
From $40.00 basic shipping fee depend on zone and country.
Registered Mail(www.singpost.com)
From $10.00 basic shipping fee depend on different zone and country.

Package

Product
Step1Product
Casing drivepipe
Step2Casing drivepipe
Anti-static bag
Step3Anti-static bag
Packaging boxes
Step4Packaging boxes
Bar-code shipping tag
Step5Bar-code shipping tag

EPM7256ERC208-20

technical specifications, attributes, parameters and parts with similar specifications to EPM7256ERC208-20.

  • Type
    Parameter
    Select All
  • Factory Lead Time

    10 Weeks

  • Mount

    Surface Mount

  • Package / Case

    QFP

  • Number of Pins

    208

  • Published

    1998

  • JESD-609 Code

    e0

  • Pbfree Code

    no

  • Moisture Sensitivity Level (MSL)

    3

  • Number of Terminations

    208

  • ECCN Code

    EAR99

  • Terminal Finish

    Tin/Lead (Sn/Pb)

  • Max Operating Temperature

    70°C

  • Min Operating Temperature

    0°C

  • Additional Feature

    CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V

  • HTS Code

    8542.39.00.01

  • Subcategory

    Programmable Logic Devices

  • Technology

    CMOS

  • Terminal Position

    QUAD

  • Terminal Form

    GULL WING

  • Peak Reflow Temperature (Cel)

    220

  • Supply Voltage

    5V

  • Terminal Pitch

    0.5mm

  • Frequency

    83.33MHz

  • Time@Peak Reflow Temperature-Max (s)

    30

  • Pin Count

    208

  • Qualification Status

    Not Qualified

  • Operating Supply Voltage

    5V

  • Temperature Grade

    COMMERCIAL

  • Max Supply Voltage

    5.25V

  • Min Supply Voltage

    4.75V

  • Number of I/O

    164

  • Memory Type

    EEPROM

  • Propagation Delay

    20 ns

  • Frequency (Max)

    90.9MHz

  • Programmable Logic Type

    EE PLD

  • Number of Gates

    5000

  • Number of Programmable I/O

    164

  • Number of Logic Blocks (LABs)

    16

  • Output Function

    MACROCELL

  • Number of Macro Cells

    256

  • JTAG BST

    NO

  • In-System Programmable

    NO

  • Height Seated (Max)

    4.1mm

  • Length

    28mm

  • Width

    28mm

  • RoHS Status

    RoHS Compliant

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