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  • EPM5192JC-2

EPM5192JC-2

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Manufacturer No:

EPM5192JC-2

Manufacturer:

Altera

HK JDW NO:

2936-EPM5192JC-2

Package:

-

Datasheet:

-

Description:

5V 1.27mm PMIC 5V

Quantity:

In Stock : 999

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EPM5192JC-2 Overview


There are 192 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).There are 64 I/Os on the board.It is programmed to terminate devices at [0].QUADis the terminal position of this electrical part.There is 5V voltage supply for this device.This part is included in Programmable Logic Devices.There are 84 pins on the chip.When using this device, LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCKis also available.In order for the device to operate, it requires 5V power supplies.5.25Vrepresents the maximal supply voltage (Vsup).The status of input signals is determined by 7dedicated inputs.A supply voltage (Vsup) of greater than 4.75V should be used.This device should not have an clock frequency greater than 50MHz.It is possible to classify programmable logic as UV PLD.Operating temperatures should not exceed 70°C.

EPM5192JC-2 Features


64 I/Os
84 pin count
5V power supplies

EPM5192JC-2 Applications


There are a lot of Altera EPM5192JC-2 CPLDs applications.

  • Address decoding
  • Auxiliary Power Supply Isolated and Non-isolated
  • Code converters
  • Configurable Addressing of I/O Boards
  • Protection relays
  • Digital designs
  • Multiple DIP Switch Replacement
  • Software Configuration of Add-In Boards
  • USB Bus
  • PLC analog input modules
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EmailEmail for receiving inquiries: jindawei@hkjdwchip.com

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Package

Product
Step1Product
Casing drivepipe
Step2Casing drivepipe
Anti-static bag
Step3Anti-static bag
Packaging boxes
Step4Packaging boxes
Bar-code shipping tag
Step5Bar-code shipping tag

EPM5192JC-2

technical specifications, attributes, parameters and parts with similar specifications to EPM5192JC-2.

  • Type
    Parameter
    Select All
  • Surface Mount

    YES

  • JESD-609 Code

    e0

  • Pbfree Code

    no

  • Number of Terminations

    84

  • Terminal Finish

    Tin/Lead (Sn/Pb)

  • Additional Feature

    LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK

  • HTS Code

    8542.39.00.01

  • Subcategory

    Programmable Logic Devices

  • Technology

    CMOS

  • Terminal Position

    QUAD

  • Terminal Form

    J BEND

  • Peak Reflow Temperature (Cel)

    220

  • Supply Voltage

    5V

  • Terminal Pitch

    1.27mm

  • Time@Peak Reflow Temperature-Max (s)

    30

  • Pin Count

    84

  • JESD-30 Code

    S-CQCC-J84

  • Qualification Status

    Not Qualified

  • Operating Temperature (Max)

    70°C

  • Supply Voltage-Max (Vsup)

    5.25V

  • Power Supplies

    5V

  • Temperature Grade

    COMMERCIAL

  • Supply Voltage-Min (Vsup)

    4.75V

  • Number of I/O

    64

  • Clock Frequency

    50MHz

  • Propagation Delay

    45 ns

  • Organization

    7 DEDICATED INPUTS, 64 I/O

  • Programmable Logic Type

    UV PLD

  • Output Function

    MACROCELL

  • Number of Macro Cells

    192

  • JTAG BST

    NO

  • Number of Dedicated Inputs

    7

  • In-System Programmable

    NO

  • Height Seated (Max)

    5.08mm

  • Length

    29.21mm

  • Width

    29.21mm

  • RoHS Status

    Non-RoHS Compliant

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