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5M240ZM100C5N

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Manufacturer No:

5M240ZM100C5N

Manufacturer:

Altera

HK JDW NO:

2936-5M240ZM100C5N

Package:

TFBGA

Datasheet:

5M240ZM100C5N

Description:

PMIC 100 Pin 118.3MHz 1.8V TFBGA

Quantity:

In Stock : 999

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5M240ZM100C5N Overview


There are 192 macro cells, which provide radio coverage via high-power cell towers, antennas or masts in a mobile phone network.In the TFBGApackage, you will find it.There are 79 I/Os on the board.Devices are programmed with terminations of [0].This electrical component has a terminal position of 0.Power is supplied by a voltage of 1.8V volts.This part is part of the family [0].With 100pins programmed, the chip is ready to use.This device can also display [0].High efficiency requires a voltage supply of [0].Data storage is performed using [0].It is mounted by Surface Mount.The device has a pinout of [0].In this case, the maximum supply voltage is 1.89V.Normally, it operates with a voltage of 1.71VV as its minimum supply voltage.Currently, there are 79 Programmable I/Os available.There is a maximum frequency of 118.3MHz.In order to operate, the temperature should be higher than 0°C.It is recommended that the operating temperature be below 85°C.The logic block consists of 8 l logic blocks (LABs).A fundamental building block consists of 240logic elements/cells.It should be below 152MHzat the maximal frequency.In the devices, there is a memory of 1kBthat can be used to store programs and data.

5M240ZM100C5N Features


TFBGA package
79 I/Os
100 pin count
100 pins
8 logic blocks (LABs)

5M240ZM100C5N Applications


There are a lot of Altera 5M240ZM100C5N CPLDs applications.

  • Software-driven hardware configuration
  • State machine design
  • Programmable power management
  • Cross-Matrix Switch
  • ToR/Aggregation/Core Switch and Router
  • ROM patching
  • ANALOG-TO-DIGITAL CONVERTOR (ADC)
  • SUPERVISORY FUNCTION (LVD AND WATCHDOG)
  • Configurable Addressing of I/O Boards
  • Pattern recognition
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EmailEmail for receiving inquiries: jindawei@hkjdwchip.com

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FedEx International, 5-7 business days.
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Payment Method

The fee is charged according to the rule of PayPal.
East West Bank charge US$30.00 banking fee.
The fee is charged according to the rule of PayPal.
Western Union charge US$0.00 banking fee.

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UPS(www.ups.com)
From $40.00 basic shipping fee depend on zone and country.
FedEx(www.fedex.com)
From $40.00 basic shipping fee depend on zone and country.
Registered Mail(www.singpost.com)
From $10.00 basic shipping fee depend on different zone and country.

Package

Product
Step1Product
Casing drivepipe
Step2Casing drivepipe
Anti-static bag
Step3Anti-static bag
Packaging boxes
Step4Packaging boxes
Bar-code shipping tag
Step5Bar-code shipping tag

5M240ZM100C5N

technical specifications, attributes, parameters and parts with similar specifications to 5M240ZM100C5N.

  • Type
    Parameter
    Select All
  • Factory Lead Time

    12 Weeks

  • Mount

    Surface Mount

  • Package / Case

    TFBGA

  • Number of Pins

    100

  • Published

    2003

  • JESD-609 Code

    e1

  • Pbfree Code

    yes

  • Part Status

    Active

  • Number of Terminations

    100

  • ECCN Code

    EAR99

  • Terminal Finish

    TIN SILVER COPPER

  • Max Operating Temperature

    85°C

  • Min Operating Temperature

    0°C

  • Additional Feature

    YES

  • Subcategory

    Programmable Logic Devices

  • Technology

    CMOS

  • Terminal Position

    BOTTOM

  • Terminal Form

    BALL

  • Peak Reflow Temperature (Cel)

    260

  • Supply Voltage

    1.8V

  • Frequency

    118.3MHz

  • Time@Peak Reflow Temperature-Max (s)

    40

  • Pin Count

    100

  • Operating Supply Voltage

    1.8V

  • Temperature Grade

    OTHER

  • Max Supply Voltage

    1.89V

  • Min Supply Voltage

    1.71V

  • Memory Size

    1kB

  • Operating Supply Current

    25μA

  • Number of I/O

    79

  • Nominal Supply Current

    25μA

  • Memory Type

    FLASH

  • Propagation Delay

    7.5 ns

  • Frequency (Max)

    152MHz

  • Number of Logic Elements/Cells

    240

  • Number of Programmable I/O

    79

  • Number of Logic Blocks (LABs)

    8

  • Speed Grade

    5

  • Output Function

    MACROCELL

  • Number of Macro Cells

    192

  • JTAG BST

    YES

  • In-System Programmable

    YES

  • Height

    1.05mm

  • Length

    6mm

  • Width

    6mm

  • Radiation Hardening

    No

  • REACH SVHC

    No SVHC

  • RoHS Status

    RoHS Compliant

  • Lead Free

    Lead Free

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