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  • EPM7512BTC144-10

EPM7512BTC144-10

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Manufacturer No:

EPM7512BTC144-10

Manufacturer:

Altera

HK JDW NO:

2936-EPM7512BTC144-10

Package:

TQFP

Datasheet:

EPM7512BTC144-10

Description:

0.5mm PMIC 144 Pin 125MHz 2.5V TQFP

Quantity:

In Stock : 999

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EPM7512BTC144-10 Overview


There are 512 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is embedded in the TQFP package.The device is programmed with 120 I/Os.144terminations are programmed into the device.As the terminal position of this electrical part is [0], it serves as an important access point for passengers or freight.Power is supplied by a voltage of 2.5V volts.The part is included in Programmable Logic Devices.There are 144pins on the chip.It is also possible to find YESwhen using this device.10000gates are used to construct digital circuits.A high level of efficiency can be achieved by maintaining the supply voltage at [0].In order to store data, EEPROMis used.It is mounted by Surface Mount.It is designed with 144 pins.In this case, the maximum supply voltage is 2.625V.With a minimal supply voltage of [0], it operates.There are 36 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. You can achieve 125MHzfrequencies.It is recommended that the operating temperature exceeds 0°C.It is recommended that the operating temperature be below 70°C.The logic block consists of 32 l logic blocks (LABs).It should be below 163.9MHzat the maximal frequency.Programmable logic types are divided into EE PLD.

EPM7512BTC144-10 Features


TQFP package
120 I/Os
144 pin count
144 pins
32 logic blocks (LABs)

EPM7512BTC144-10 Applications


There are a lot of Altera EPM7512BTC144-10 CPLDs applications.

  • Bootloaders for FPGAs
  • Interface bridging
  • Reset swapping
  • Power automation
  • Synchronous or asynchronous mode
  • SUPERVISORY FUNCTION (LVD AND WATCHDOG)
  • Code converters
  • State machine design
  • ON-CHIP OSCILLATOR CIRCUIT
  • Voltage level translation
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EmailEmail for receiving inquiries: jindawei@hkjdwchip.com

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3. RFQ (Request for Quotations)

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Payment Method

The fee is charged according to the rule of PayPal.
East West Bank charge US$30.00 banking fee.
The fee is charged according to the rule of PayPal.
Western Union charge US$0.00 banking fee.

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From $40.00 basic shipping fee depend on zone and country.
Registered Mail(www.singpost.com)
From $10.00 basic shipping fee depend on different zone and country.

Package

Product
Step1Product
Casing drivepipe
Step2Casing drivepipe
Anti-static bag
Step3Anti-static bag
Packaging boxes
Step4Packaging boxes
Bar-code shipping tag
Step5Bar-code shipping tag

EPM7512BTC144-10

technical specifications, attributes, parameters and parts with similar specifications to EPM7512BTC144-10.

  • Type
    Parameter
    Select All
  • Mount

    Surface Mount

  • Package / Case

    TQFP

  • Number of Pins

    144

  • Published

    1998

  • JESD-609 Code

    e0

  • Pbfree Code

    no

  • Moisture Sensitivity Level (MSL)

    3

  • Number of Terminations

    144

  • ECCN Code

    3A991

  • Terminal Finish

    Tin/Lead (Sn/Pb)

  • Max Operating Temperature

    70°C

  • Min Operating Temperature

    0°C

  • Additional Feature

    YES

  • HTS Code

    8542.39.00.01

  • Subcategory

    Programmable Logic Devices

  • Technology

    CMOS

  • Terminal Position

    QUAD

  • Terminal Form

    GULL WING

  • Peak Reflow Temperature (Cel)

    220

  • Supply Voltage

    2.5V

  • Terminal Pitch

    0.5mm

  • Frequency

    125MHz

  • Time@Peak Reflow Temperature-Max (s)

    30

  • Pin Count

    144

  • Operating Supply Voltage

    2.5V

  • Temperature Grade

    COMMERCIAL

  • Max Supply Voltage

    2.625V

  • Min Supply Voltage

    2.375V

  • Number of I/O

    120

  • Memory Type

    EEPROM

  • Propagation Delay

    10 ns

  • Turn On Delay Time

    10 ns

  • Frequency (Max)

    163.9MHz

  • Programmable Logic Type

    EE PLD

  • Number of Gates

    10000

  • Number of Programmable I/O

    36

  • Number of Logic Blocks (LABs)

    32

  • Speed Grade

    10

  • Output Function

    MACROCELL

  • Number of Macro Cells

    512

  • JTAG BST

    YES

  • In-System Programmable

    YES

  • Height Seated (Max)

    1.6mm

  • Length

    20mm

  • Width

    20mm

  • Radiation Hardening

    No

  • RoHS Status

    RoHS Compliant

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