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Home Home Integrated Circuits (ICs) CPLDs EPM5130GM883B2
EPM5130GM883B2
  • EPM5130GM883B2
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EPM5130GM883B2

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Manufacturer No:

EPM5130GM883B2

Manufacturer:

Altera

HK JDW NO:

2936-EPM5130GM883B2

Package:

-

Datasheet:

-

Description:

5V 2.54mm PMIC 5V

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In Stock : 999

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EPM5130GM883B2 Overview


There are 128 macro cells, which provide radio coverage via high-power cell towers, antennas or masts in a mobile phone network.As a result, it has 64 I/O ports programmed.There is a 100terminations set on devices.This electrical component has a terminal position of 0.The power source is powered by 5Vvolts.There is a part included in Programmable Logic Devices.It has 100pins programmed.When using this device, LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCKis also available.The system runs on a power supply of 5V watts.5.5Vrepresents the maximal supply voltage (Vsup).The status of input signals is determined by 19dedicated inputs.In order to operate properly, the supply voltage (Vsup) should be greater than 4.5V.Its clock frequency should not exceed 40MHz.Programmable logic types are divided into UV PLD.It is recommended that the operating temperature remain below 125°C.Ideally, the operating temperature should be [0].

EPM5130GM883B2 Features


64 I/Os
100 pin count
5V power supplies

EPM5130GM883B2 Applications


There are a lot of Altera EPM5130GM883B2 CPLDs applications.

  • Auxiliary Power Supply Isolated and Non-isolated
  • PULSE WIDTH MODULATION (PWM)
  • Software-driven hardware configuration
  • State machine design
  • Wide Vin Industrial low power SMPS
  • POWER-SAVING MODES
  • Power up sequencing
  • LED Lighting systems
  • Boolean function generators
  • Field programmable gate
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Package

Product
Step1Product
Casing drivepipe
Step2Casing drivepipe
Anti-static bag
Step3Anti-static bag
Packaging boxes
Step4Packaging boxes
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Step5Bar-code shipping tag

EPM5130GM883B2

technical specifications, attributes, parameters and parts with similar specifications to EPM5130GM883B2.

  • Type
    Parameter
    Select All

  • Surface Mount

    NO

  • JESD-609 Code

    e0

  • Number of Terminations

    100

  • ECCN Code

    3A001.A.2.C

  • Terminal Finish

    Tin/Lead (Sn/Pb)

  • Additional Feature

    LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK

  • HTS Code

    8542.39.00.01

  • Subcategory

    Programmable Logic Devices

  • Technology

    CMOS

  • Terminal Position

    PERPENDICULAR

  • Terminal Form

    PIN/PEG

  • Supply Voltage

    5V

  • Terminal Pitch

    2.54mm

  • Pin Count

    100

  • JESD-30 Code

    S-CPGA-P100

  • Qualification Status

    Not Qualified

  • Operating Temperature (Max)

    125°C

  • Operating Temperature (Min)

    -55°C

  • Supply Voltage-Max (Vsup)

    5.5V

  • Power Supplies

    5V

  • Temperature Grade

    MILITARY

  • Supply Voltage-Min (Vsup)

    4.5V

  • Number of I/O

    64

  • Clock Frequency

    40MHz

  • Propagation Delay

    45 ns

  • Organization

    19 DEDICATED INPUTS, 64 I/O

  • Programmable Logic Type

    UV PLD

  • Screening Level

    38535Q/M;38534H;883B

  • Output Function

    MACROCELL

  • Number of Macro Cells

    128

  • JTAG BST

    NO

  • Number of Dedicated Inputs

    19

  • In-System Programmable

    NO

  • Height Seated (Max)

    3.81mm

  • Length

    33.528mm

  • Width

    33.528mm

  • RoHS Status

    Non-RoHS Compliant

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