MA803AS2

Description

MA803AS2 is a 80C51-based high-performance 1-T structure of single-chip microprocessors, each instruction requires 1 to 7 clock signals (8051 than the standard fast 6 to 7 times), compatible with the 8051 instruction set. So in the standard 8051 has the same processing capacity of the case, MA803 only need very low operating speed, and thus can greatly reduce the power consumption.

The MA803 has 15.5K bytes of built-in flash memory for code and data. Flash memory can be programmed in-system (ISP). At the same time, it also provides in-application programming (IAP) capabilities. ISP allows users to download new code without removing the microcontroller from the product; IAP means that the microcontroller can write non-volatile data in Flash while the application is running. These functions are programmed by the built-in charge pump to provide high voltage.

MA803AS2 retains the basic features of the standard 80C52: 512 bytes of random access memory, 23 I / O ports, two external interrupts, and two timer / counters. A PCA timer, an SPI interface, a one-time-enabled watchdog WDT, a 10-bit ADC, a low-level reconnaissance LVD, an enhanced multiprocessor communication and improved speed universal string Line port (EUART).

The MA803 has two power-saving modes to reduce power consumption. In Idle mode, the CPU is frozen and the peripheral module and interrupt system remain active. In Power-down mode, the contents of RAM and Special Function Registers (SFRs) are saved and all other functions are terminated. Most importantly, the microcontroller in power-down mode can be woken up by an external interrupt.

Features

1. 1-T 80C51 central processing unit
2. The MA803 has 15.5K bytes of Flash ROM
(1) 13.5KB for the AP code program space
(2) 1KB for the IAP data Flash space
(3) Flash memory access to provide code protection
3. On-chip 512-byte data RAM
4. Two 16-bit Timer / Event Counters: Timer 0, Timer 1,
5. 7 interrupt sources, four priority interrupt capability
6. Enhanced UART, support frame error detection hardware address recognition
7. 15-bit watchdog timer Watch-Dog-Timer. 8-bit divide by CPU or power-up one-time enable
8. SPI Interface (Master / Slave Mode)
9. A PCA (Programmable Counter Array)
(1) Capture mode
(2) 16-bit software timer mode
(3) high-speed output mode
(4) PWM (Pulse Width Modulator) mode
10. 8-channel 10-bit ADC,