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FII24N17AH1
FII24N17AH1
415-FII24N17AH1
i4-Pac™-5
FII24N17AH1 datasheet pdf and Transistors - IGBTs - Arrays product details from IXYS stock available at HK JDW
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FII24N17AH1 Description
The MT90869 has two data ports, the Backplane, and the Local port. The Backplane port has two modes of operation, either 32 input and 32 output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s, in any combination, or 16 input and 16 output streams operated at 32.768 Mb/s. The Local port has 32 input and 32 output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s, in any combination. The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). In Connection Mode the contents of the connection memory define, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other ST-BUS devices. The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing for both the backplane port and the local port. The device will automatically detect whether an ST-BUS or a GCI-BUS style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the establishment of full switch functionality. During this period the frame format is determined before switching begins. The device provides FP8o, FP16o, C8o, and C16o outputs to support external devices connected to the local port. Subrata switching is accomplished by oversampling (i.e., 1-bit switching can be accomplished by sampling a 2 Mb/s stream at 16 Mbps). Refer to MSAN 175. A non-multiplexed Motorola microprocessor port allows the programming of the various device operation modes and switching configurations. The microprocessor port provides access for Register read/write, Connection Memory read/write, and Data Memory read-only operations. The port has a 15-bit address bus, a 16-bit data bus, and 4 control signals. The microprocessor may monitor channel data in the backplane and local data memories.
FII24N17AH1 Features
16,384-channel x 16,384-channel non-blocking unidirectional switching. The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 64 stream inputs and 64 stream outputs
8,192-channel x 8,192-channel non-blocking Backplane to Local stream switch
8,192-channel x 8,192-channel non-blocking Local to Backplane stream switch
8,192-channel x 8,192-channel non-blocking Backplane input to Backplane output switch
8,192-channel x 8,192-channel non-blocking Local input to Local output stream switch
Rate conversion on all data paths, Backplane to Local, Local to Backplane, Backplane to Backplane, and Local to Local streams
The Backplane port accepts 32 ST-BUS streams with data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s in any combination or a fixed allocation of 16 streams at 32.768 Mb/s
The local port accepts 32 ST-BUS streams with data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s, in any combination
Per-stream channel and bit delay for Local input streams
Per-stream channel and bit delay for Backplane input streams
Per-stream advancement for Local output streams
Per-stream advancement for Backplane output streams
Constant throughput delay for frame integrity
Per-channel high impedance output control for Local and Backplane streams
Per-channel driven-high output control for local and backplane streams
High impedance-control outputs for external drivers on the backplane and local port
Per-channel message mode for local and backplane output streams
Connection memory block programming for fast device initialization
BER testing for local and backplane ports.
Automatic selection between ST-BUS and GCI-BUS operation
Non-multiplexed Motorola microprocessor interface
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
Memory Built-In-Self-Test (BIST), controlled via microprocessor registers
1.8 V core supply voltage
3.3 V I/O supply voltage
5 V tolerant inputs, outputs, and I/Os
Per stream substrate switching at 4-bit, 2-bit, and 1-bit depending on stream data rate
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FII24N17AH1
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