China's Fully Independent and Controllable Chiplet High-Speed Serial Port Standard is Officially Released!
In February 2023, at the Xi'an Qin Chuangyuan Artificial Intelligence Cutting-edge Scientific and Technological Achievements Conference, Academician Yao Qizhi of Tsinghua University represented the China Chiplet Industry Alliance and jointly released the "Chiplet Chiplet Interconnect Interface Standard"-Advanced Cost-driven Chiplet Interface (ACC), this standard is led by the Cross Information Core Technology Research Institute and jointly drafted by the China Chiplet Industry Alliance. At present, the standard involves related group standards and industry standards are under application.
As Moore's Law is gradually approaching the physical and commercial limits, chip design concepts based on Chiplets have gradually become an industry development trend in the post-Moore era. In September 2020, at the Xi'an Hard Technology Conference, the China Chiplet Industry Alliance (China ChipLet League (CCLL)) was launched, aiming to be guided by national industrial policies, driven by the market, and take enterprises as the main body to build industrial ecological cooperation Platform, jointly formulate Chiplet interconnection standards, jointly build an open platform for Chiplet technology, and build my country's thriving Chiplet industry ecology.
The domestic semiconductor industry is still in the development stage, especially under the current international situation, it will also be in the catch-up stage for a long time, and there is still a certain gap compared with the international leading technology level in all links of the industrial chain. In the wafer manufacturing process: due to various factors, it is difficult for domestic fabs to achieve large-scale mass production of 14nm and below advanced process nodes in the short term, especially in the field of high-performance computing. The overall yield rate of large-area chips is still relatively low. At a low level, under the current trend, it is even necessary to consider a cost-controllable business path through process retracement. In the packaging and testing process: the domestic traditional packaging technology is relatively mature, and some achievements have been made in 2.5D advanced packaging technology. However, the ABF substrate as a key material still needs to rely on overseas supply chains. Compared with the first-line international level, the connection density, line width and line spacing, through-hole via-hole blind hole technology and burr control that the level pays more attention to are still far behind.
Against the above-mentioned industrial background, the industrialization of Chiplets in China also faces many difficulties in implementation: For example, in terms of interfaces: At present, the focus of domestic research and development is mainly on low-speed interface standards (such as UCIe), which have good delay performance but require advanced packaging and carrier boards. Higher, and the packaging cost is higher, commercialization is difficult; while the core technology of high-speed interface is mastered by overseas IP manufacturers, and there is no effective demand and product definition in China. In terms of chip products: At present, domestic chip products are relatively limited. Although many companies have increased investment in IP chip granulation and interface chip granulation and gradually productized them, due to the lack of standardized testing and integration processes for Chiplet, and The needs of various scenarios in the downstream industry are relatively diversified, and there is no commercially viable Chiplet product direction yet.
We believe that under the current situation and environment, the domestic semiconductor industry needs to make breakthroughs in Chiplets. The challenges and opportunities it faces lie in: how to integrate existing relatively backward manufacturing processes, advanced packaging technologies that are still under development, and related core materials. Based on the supply chain, products that meet performance expectations and have controllable costs make Chiplets truly commercially viable. In this context, the development of China's chiplet industry requires upstream and downstream to jointly establish an industrial ecology, drive upstream resource input with downstream demand, exchange cost advantages with mass production economies of scale, and ultimately form a virtuous development cycle.
In 2022, Intel, AMD, TSMC and other global top ten related corporate giants established the UCIe alliance, providing a chip interconnection standard with a bandwidth of up to 32G, suitable for 2.5D and 3D advanced packaging (such as Intel EMIB, TSMC CoWoS, etc.). The "Chiplet Interconnection Interface Standard" ACC released by the China Chiplet Industry Alliance this time is a high-speed serial port standard with a bandwidth of 32G or more, focusing on the optimization and applicability of the domestic substrate and packaging supply chain system, as well as cost control.
The difference in applicability between the two mainly lies in the industry-oriented fields and the acceptable cost structure of end-user scenarios: in the field of pursuing ultra-high-performance computing, although the mass production cost of advanced packaging required by UCIe may account for 60% of the total cost of the chip. %~70% or even higher, but the way of small-area chip interconnection can effectively solve the pain point of large-area chip yield under advanced technology, and has high commercial value in the case of large shipments. However, in many downstream areas where costs are sensitive, shipments are limited, supply chain capabilities are weak, and supply guarantee requirements are high, the adoption of the ACC standard can better meet the needs of commercial feasibility.
Generally speaking, China's Chiplet industry chain and final Chiplet products must be integrated and participate in global competition. Therefore, in terms of standard applicability, it should also be tolerant to competition, compatibility, and integration between standards. At present, since UCIe does not define standards for frequencies above 32GHz, and ACC does not define standards for frequencies below 32GHz, the two are compatible at frequencies of 32GHz.
From a technical perspective, the ACC standard, as a high-speed serial port standard, is suitable for multi-die encapsulation with a fixed and predictable data stream structure. If the structure of the data flow can be predicted in advance, the data can be moved in advance. Data that is sensitive to bandwidth and latency can be optimized through data pre-reading and compilation.
As mentioned above, from the perspective of application fields, the ACC standard is more suitable for various heterogeneous computing scenarios, such as various AI acceleration products, GPUs, FPGAs, and multi-core CPU Dies that have been interconnected and interact with other heterogeneous modules. For the coherence interaction scenario where the data flow is unpredictable in the interconnection of multiple single-core CPUs, the delay of the ACC standard has a great impact on the overall performance.
At present, mainstream semiconductor giants at home and abroad have internal interconnection standards adopted according to their own product needs, but none of them have been authorized to be used externally. The ACC standard released by the China Chiplet Industry Alliance is to follow the trend of industry development, with commercial implementation as the main goal, through Differentiated technical advantages and attractive licensing prices have finally been widely used and promoted in the market.
Unlike UCIe, which is based on the global supply chain and advanced packaging, the ACC standard is optimized at the interface level based on domestic substrate and packaging capabilities, and takes cost control as the main entry point. The ACC standard has promoted the research and development of related companies within the alliance, and related companies will launch corresponding interface products based on the ACC standard in the near future, and use this to promote chiplet-based heterogeneous integration related solutions to solve the domestic demand for large computing power SoC market is common There are pain points such as long development cycle, high risk, slow iteration, and large investment.
On the basis of this co-construction standard, all semiconductor design companies in the industry can join hands with the top customer groups in the industry, take the project as the starting point, further jointly build projects to enrich the chiplet chip library, and promote the application of chiplet solutions in various business scenarios, so that Realize the accelerated implementation of the domestic chiplet solution.
Need Help?
